1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory device such as an EPROM (erasable programmable read only memory), EEPROM (electrically erasable programmable read only memory) and a flash memory. The present invention also relates to a method of manufacturing such a nonvolatile semiconductor memory device.
2. Description of the Related Arts
High-density nonvolatile memory devices have been receiving much attention for application in many fields. One of the most important factors is the low cost of the reduced size of each memory cell. However, it is very difficult to shrink the cell size in the fabrication of nonvolatile memory cells when the conventional local oxidation (LOCOS) isolation technique is used. The isolation structure formed by this technique has a very large dimension and thus limits the miniaturization of the memory cells.
Another isolation technique called shallow trench isolation (STI) has been introduced to the fabrication of nonvolatile memory devices to reduce the cell size. The conventional field oxides are replaced by STI structures so that the device integration can be effectively improved. However, as component dimensions continue to shrink, the surface area of floating gates also shrinks. This leads directly to a decrease in capacitance of the effective capacitor formed between the floating gate layer and the control gate layer. This decrease in effective capacitance results in a reduction of the coupling ratio, which is a parameter that describes the coupling to floating gate of the voltage applied to control gate. The poorly-coupled voltage to floating gate limits the programming and accessing speed characteristics of the memory device.
The coupling ratio Cp is defined by:   Cp  =      Ccf          Ccf      +      Cfs      
where Ccf is capacitance between the control gate and the floating gate; and Cfs is capacitance between the floating gate and the semiconductor substrate.
In order to gain programming and accessing speeds in nonvolatile memories, many attempts have been done to increase the coupling ratio. It can be understood from the above equation that when the capacitance Ccf between the control gate and the floating gate increases, the coupling ratio Cp increases. Therefore, the coupling ratio Cp is generally increased by increasing the capacitor area between the floating gate and control gate, which increases the capacitance Ccf, and therefore the coupling ratio Cp. However, such attempts often come with the additional expense or limitation in processing the device. For example, U.S. Pat. No. 6,171,909 discloses a method for forming a stacked gate of a flash memory cell. The coupling ratio of the stacked gate is increased by forming a conductive spacer. The conductive spacer, which is a portion of the floating gate, increases the capacitor area between the floating gate and control gate. Nevertheless, this method is quite complicated and incurs additional cost. Accordingly, the coupling ratio generally cannot be improved in an easy and cost effective manner.
In the present invention, a nonvolatile semiconductor memory device with an increased coupling ratio is disclosed. This is accomplished by reducing the capacitance Cfs between the floating gate and the semiconductor substrate, rather than by increasing the capacitance Ccf between the control gate and the floating gate.
An object of the invention is to provide a nonvolatile semiconductor memory device having a high coupling ratio.
Another object of the invention is to provide a simple method of manufacturing a nonvolatile semiconductor memory device with a high coupling ratio.
The above and other objects and advantages are achieved by reducing the capacitor area between the floating gate and the semiconductor substrate by a single thermal oxidation process. The smaller capacitor area decreases the capacitance Cfs between the floating gate and the semiconductor substrate, and thus obtains a higher coupling ratio.
According to an aspect of the invention, there is provided a nonvolatile memory device comprising: a semiconductor substrate having shallow trench isolation (STI) formed therein and active regions defined; a floating gate provided on the active regions with a first dielectric layer interposed; and a control gate formed on the floating gate with a second dielectric layer interposed therebetween; wherein the width of the floating gate is narrower than the active regions when viewed in transverse cross-section. Optionally, the device further includes a lightly doped region in the substrate at positions which are not covered by the floating gate.
According to another aspect of the invention, there is provided a method for forming a nonvolatile memory device comprising the steps of: forming a gate oxide layer on a silicon substrate; forming a first polysilicon layer on the gate oxide layer for serving as a floating gate of the memory device; patterning the first polysilicon layer, the gate oxide layer, and the substrate to form trenches in the substrate and to form a floating gate on an active region separated by the trenches with a patterned gate oxide layer interposed; and thermally oxidizing the first polysilicon layer, thereby narrowing the width of the floating gate relative to the active region.
To complete the fabrication of the memory device, the method may further includes the following steps: forming isolation oxide in the trenches to form shallow trench isolation (STI); optionally forming a lightly doped region in the substrate at positions which are not covered by the floating gate; and sequentially forming an interpoly oxide layer and a second polysilicon layer for serving as a control gate of the memory device over the substrate.